The present invention relates generally to processes for fabricating insulated gate semiconductor devices and more particularly, to a process for fabricating a lateral insulated gate transistor such as the improved lateral insulated gate transistor disclosed in the aforementioned patent application Ser. No. 935,368. Heretofore, lateral insulated gate semiconductor devices have been commonly fabricated using 14 different masks. In a typical 14 mask process, a first mask is used to establish a charge control region, a second mask is used to establish a buried layer, a third mask is used for a P isolation region/sinker, a fourth mask is used to establish a buffer region, a fifth mask is used to establish the active area of the device, a sixth mask is used to establish a gate electrode, a seventh mask is used to establish a base region, an eighth mask is used to establish an anode region, a ninth mask is used to establish an N+ source region, a tenth mask is used to establish a SIPOS window, an eleventh mask is used to establish a SIPOS layer, a twelfth mask is used to establish a contact window, a thirteenth mask is used to pattern the contact metals and a fourteenth mask is used to pattern the overglass protection. It has been recognized that in devices not requiring SIPOS protection, the tenth and eleventh masks for providing SIPOS oxide deposition can be eliminated and thus only 12 masks are required to establish a lateral insulated gate device.
As known to those skilled in the art, each mask step adds additional costs to the semiconductor processing and establishes one more step in which a process failure can occur. Thus, processes which employ a large number of masks and hence large number of steps, exhibit a higher cost and a lower yield than processes which employ a fewer number of masks and a fewer number of mask steps.